`timescale 1ns / 1ps
module rom_dac_in(
    input fpga_dac_clk_245p76,
    input pl_rst,
    input dac_data_ready,
    
    output [255 : 0] dac_data,
    output dac_data_valid
    );
    
    reg [9 : 0] addra = 0;
    
    blk_mem_gen_0 data (
    .clka(fpga_dac_clk_245p76),    // input wire clka
    .addra(addra),  // input wire [9 : 0] addra
    .douta(dac_data)  // output wire [255 : 0] douta
    );
    
    always @(posedge fpga_dac_clk_245p76)
    begin
        if(pl_rst || ~dac_data_ready)
            addra <= 0;
        else
            addra <= addra + 1;
    end
    assign dac_data_valid = ~pl_rst && dac_data_ready;
    
endmodule
